Synopsys Analog, Mixed Signal and Full Custom Design & Verification Flow
Онлайн
16 Июля 2020 г., 14:00-15:30 (Мск)
Вебинар будет посвящен обзору инструментов Synopsys для разработки дизайна аналоговых интегральных схем и СнК, включающих аналоговую часть.
AGENDA
Custom Compiler Schematic Capture and Simulation Environment
An overview of Custom Compiler’s comprehensive design capture, simulation and analysis environment, including Powerful Results Viewer, Advanced Monte Carlo and Documentation generation.
SPICE simulation
Synopsys SPICE simulators set an industry benchmark for accuracy. From HSPICE which used as the golden accuracy standard at most foundries, FineSim which enables high performance and precision analog/RF simulation, to CustomSim which provides accurate full chip analog simulation for mixed signal chips.
Mixed signal Verification
VCS AMS, Synopsys’ mixed-signal verification environment, enables digital verification techniques such as System Verilog assertions, UVM and UPF to be used on the analog as well as the digital parts of a design. Therefore enabling a true mixed signal verification of a system.
Custom Compiler Layout Environment
Custom Compiler’s advanced layout features and innovative methodologies enable a step change in productivity for complex layout
Докладчики: Damian Roberts и Andrew Milne. Инженеры по сопровождению маршрута проектирования аналоговых и смешанных схем компании Synopsys
Краткая информация по инструментам:
https://www.synopsys.com/implementation-and-signoff/custom-design-platform.html
РЕГИСТРАЦИЯ
https://engineering.timepad.ru/event/1354093/
Информация о мероприятии: https://mailchi.mp/81d4274b7df8/synopsys-ams-design-webinar
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